Soft Machines, a well-funded startup ($175 million to date) that came out of stealth last year, announced its “Virtual Instruction Set Computing” (VISC) architecture, which promises 2-4x higher performance/Watt compared to existing CPU designs.
Current CPU architectures scale performance by using wider architectures and out-of-order execution to improve instruction-level parallelism (ILP) and by adding additional cores to improve thread-level parallelism (TLP). These techniques are limited by Amdahl’s law, however, leading to larger, more power-hungry processors. The challenges of multi-threaded programming, which is necessary to extract the full benefit of multiple CPU cores, also places limits on achieving high levels of TLP.
In order to improve performance/Watt scaling, Soft Machines is taking a different approach. Its architecture uses “virtual cores” (VC) that shift the burden of thread scheduling and synchronization from the software programmer and operating system to the hardware itself. With VISC, a single thread is not restricted to a single core like traditional multiprocessor designs. Instead, it gets broken down into smaller threadlets by the VCs and executes on multiple underlying physical cores (PC). By using the available execution units more efficiently, the VISC architecture, in theory, can maintain high performance even when using smaller, simpler physical cores, which reduces power consumption. Another advantage of this technique is that single-threaded applications can execute on multiple physical cores.
Soft Machines claimed that its virtual cores can either increase the performance/Watt by 2-4x at the same power consumption level, or they can decrease the power consumption by 4x at the same performance level relative to existing designs.
Unlike ARM, which licenses its core design IP, or Intel, which manufactures its own cores and SoCs, Soft Machines will partner with other companies to create custom processors and SoCs.
The company said that the first processor, called “Shasta,” will tape-out on TSMC’s 16FF+ processing node in mid-2016. That means we probably won’t see a shipping product until at least a year later.
Shasta will contain two physical cores up to 2 GHz each, with 1MB of cache per core, and a high-speed 256-bit read/write system interface unit. Shasta will use a custom 64-bit ISA but will support guest ISAs as well. The corresponding SoC, which will contain up to two Shasta processors and 2-4 virtual cores, is called “Mojave” and will tape-out in Q3 2016. The chips are designed to scale up from mobile to server markets.
In 2017, the company’s roadmap includes the “Shasta+” processor with the corresponding “Tabernas” SoC. Shasta+ will have 1-4 virtual cores for 2 physical cores, or 2-8 virtual cores for 4 physical cores, and it will include additional architectural enhancements. The processor will be made on a 10nm process node.
For 2018, the company will work on the “Tahoe” processor with 1-8 virtual cores and 4 physical cores, as well as a 2-16VC/8C variant. The corresponding SoC will be called “Ordos.”